1. Field of the Invention
The present invention relates to an integrated circuit for sensing stored information of a non-volatile memory (NVM). In particular, the present invention relates to circuitry and operating method that are applied to sense information stored on NVM devices (e.g., electrically erasable programmable read-only memory (EEPROM), read only memories (ROMs), phase-change memories (PCMs), and magneto-resistive random memories (MRAMs)).
2. Discussion of the Related Art
In an integrated memory circuit, a readout circuitry detects and determines the content stored in a selected NVM cell. In many NVM cells, the stored information is represented by one of several possible values of its electrical conductance characteristics. The selected values are kept even after the NVM device's power is withdrawn or cut off. For instances, an EEPROM cell can represent its stored information by adopting in a metal-oxide-semiconductor field effect transistor (MOSFET) one of several threshold voltages. The selected threshold voltage is achieved by storing a known amount of charge in between the MOSFET's control gate and its channel. A ROM cell can represent a binary stored value by having a connection or not having a connection between a MOSFET and a bit line. A PCM represents a binary stored value by being in either a high electrical conductance state or a low electrical conductance state, according to whether a silicon layer in the device is in an amorphous phase or a polycrystalline phase. Basically, the stored information in an NVM cell can be determined by measuring an electrical conductance in the NVM cell, and by requiring that the conductance characteristics remain even after power is turned off.
Therefore, one way to read out the stored data in a selected NVM cell is to apply a bias voltage to the NVM cell and measure the resulting current. In a conventional readout scheme, e.g., using readout circuit 100 of FIG. 1, cell current from NVM cell 102 responsive to the input bias voltage on word line 101 is pre-amplified at current amplifier 103 and compared with a reference current generated by reference current generation circuit 104. The two currents may be compared using differential amplifier comparator 105. The output value of comparator 105 represents either a high NVM electrical conductance, corresponding to detecting a large resulting current, and a low NVM electrical conductance, corresponding to detecting a low resulting current. In this readout process, large steady output currents are supplied from the memory cells (e.g., NVM memory cell 102) being in a high electrical conductance state, pre-amplifier 103, differential amplifier comparator 105, and reference current circuitry 104. Large steady currents lead to a high power requirement for reading out the stored information from the NVM cell.